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Synchronous Buck Controller with Dual-Level VOUT Transition Support
POWER MANAGEMENT POWER MANAGEMENT Description
The SC475A is a versatile, constant on-time synchronous buck, pseudo-fixed-frequency, PWM controller intended for notebook computers and other battery operated portable devices. The SC475A contains all the features needed to provide cost-effective control of system elements needing voltage slewing. An integrated switch provides two resistorprogrammable DC output voltages controlled by the G0 input. The output voltage is adjustable from 0.75V to 5V. Additional features include cycle-by-cycle current limit, voltage soft-start, under-voltage protection, programmable over-current protection, soft shutdown, automatic power save and non-overlapping gate drive. The SC475A provides an enable input and a power good output which is automatically blanked during output voltage transitions. The constant on-time topology provides fast dynamic response. The excellent transient response means that SC475A based solutions require less output capacitance than competing fixed-frequency converters. Switching frequency is constant until a step in load or line voltage occurs, at which time the pulse density and frequency will increase or decrease to counter the change in output voltage. After the transient event, the controller frequency returns to steady state operation. At light loads, the automatic power save mode reduces the SC475A frequency for improved efficiency.
SC475A
Features
VOUT Programmable 0.75V to 5.25V with Integrated Transition Support VBAT Range 3V to 25V Soft Shutoff at Output Current Sense Using Low-side RDS(ON) or Resistor Sensing Adjustable Cycle-by-Cycle Valley Current Limit 325kHz Fixed-Frequency Constant On-Time for Fast Dynamic Response and Reduced Output Capacitance Automatic Smart Power Save Internal Soft-Start Over-Voltage/Under-Voltage Fault Protection Power Good Output with Transition Blanking 1A Typical Shutdown Current 500A Typical Operating Current Tiny 3x3mm, 16 Pin MLP Package Low External Part Count Industrial Temperature Range 0.85% Internal Reference 1A/3A Non-Overlapping Gate Drive with SmartDriverTM Technology High Efficiency > 90% Device is Fully WEEE and RoHS Compliant
Patent
Pending
Applications
Notebook/Sub-Notebook Graphics Voltage Controllers Tablet PCs Embedded Applications
September 25, 2006
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SC475A
POWER MANAGEMENT Typical Application Circuit
VCC C4 D1 VBAT C3 Q1 R4 G0
16
15
14 G0
C2 L1 VOUT 1 2 C1 VCC Q2 3 4
DH
ILIM
NC
13
LX BST VCC DL
EN
12 11 10 9
EN PGOOD VOUT
U1 PGOOD SC475A
RTN NC
VOUT FB
GND
5
6
7
8
R3
D0
R1
R2
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SC475A
POWER MANAGEMENT Absolute Maximum Rating
Exceeding the specifications below may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device reliability.
Parameter DH, BST to GND (DC) DH, BST to GND (transient - 100nsec max) DL to GND (DC) DL to GND (transient - 100nsec max)
Symbol
Min -0.3 -2.0 -0.3 -2.0 -0.3 -2.0 -0.3 -0.3 -0.3 -0.3
Max +30 +33 +6.0 +6.0 +25 +28 +6.0 +0.3 +6.0 VCC + 0.3 +125 +150
o
Units V V V V V V V
o o
LX to GND (DC)
LX to GND (transient - 100nsec max) BST to LX RTN to GND VCC to RTN D0, EN, FB, G0, ILIM, PGOOD, VOUT to RTN Operating Junction Temperature Range Storage Temperature Range Thermal Resistance, Junction to Ambient(1) Peak IR Reflow Temperature, (10-40sec) ESD Rating (Human Body Model) TJ TSTG
-40 -60 45
C C
JA
TPKG
C/Watt
o
+260 2
C
kV
Note: 1) Calculated from package in still air, mounted 3" to 4.5", 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.
Electrical Characteristics
Test Conditions: VBAT = 15V, VOUT = 1.5V, TA = 25 oC, 0.1% resistor dividers; VCC = 5.0V.
Parameter Input Supplies VBAT Input Voltage VCC Input Voltage VCC Shutdown Current VCC Operating Current Controller FB On-Time Threshold Output Voltage Adjust Range(1) D0 Pull-Down Resistance
(c) 2006 Semtech Corp.
Conditions Min
25C Typ Max
-40 to 85C Min Max
Units
3.0 4.5 EN = 0V FB > 0.8V 1 500
25 5.5 5 1000
V V A A
0 to 85C -40 to 85C
0.75
0.7436 0.7564 0.7425 0.7575 0.75 5.25 40 V V
D0 to RTN; G0 = RTN
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SC475A
POWER MANAGEMENT Electrical Characteristics (continued)
25C Parameter Conditions Min Regulation Line Regulation Error Load Regulation Error Timing On-Time Minimum On-Time Minimum Off-Time Maximum Duty Cycle Soft-Start Soft-Start Time Analog Inputs/Outputs VOUT Input Resistance FB Input Bias Current Current Sense Zero Crossing Detector Threshold Power Good Power Good Threshold Threshold Delay Time(1) Voltage Transition Blank Time(1) Leakage Fault Protection ILIM Source Current ILIM Comparator Offset Current Limit (Negative) Output Under-Voltage Fault LX - GND FB with Respect to Nominal 10 0 80 -30 9 -10 60 -35 11 +10 100 -25 A mV mV % G0 Transition 1% Hysteresis Typical -20% 5 32 1 -17% -23% V s clks A LX - GND 0 -7 +7 mV 500 -1 +1 k A IOUT = ILIM/2 1000 s VBAT = VOUT + 0.2 FB < 0.7V VOUT = 1.1V 250 100 350 85 80 225 275 ns ns ns % Typical Application Circuit Typical Application Circuit 0.04 0.3 %/V % Typ Max Min Max -40 to 85C Units
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SC475A
POWER MANAGEMENT Electrical Characteristics (continued)
25C Parameter Fault Protection (continued) Steady-State Over-Voltage Fault Steady-State Over-Voltage Fault Delay G0 Transition Over-Voltage Fault Smart Power Save Threshold Over-Temperature Shutdown(1) Logic Inputs/Outputs Logic Input High Voltage Logic Input Low Voltage EN Input Bias Current G0 Input Bias Current Power Good Output Low Voltage Gate Drivers Shoot-Through Protection Delay(1) DL Pull-Down Resistance DL Sink Current DL Pull-Up Resistance DL Source Current DH Pull-Down Resistance DH Pull-Up Resistance(2) DH Sink/Source Current VDL = 2.5V BST - LX = 5V BST - LX = 5V VDH = 2.5V VDL = 2.5V DH or DL Rising 30 0.8 3.1 2 1.3 2 2 1.3 4 4 4 1.6 ns A A A EN, G0 EN, G0 EN = 5V G0 = 5V RPWRGD = 10k to VCC 5 -1 0 1.2 0.4 +1 10 0.4 V V A A V FB with Respect to Nominal FB Forced 50mV Above Over-Voltage Fault Threshold FB with Respect to Nominal; Valid for 32 cycles after G0 Transition FB with Respect to Nominal Latching, >10C Hysteresis +20 5 +17 +23 % s Conditions Min Typ Max Min Max -40 to 85C Units
+50 +8 160
% % C
Notes: 1) Guaranteed by design. 2) Semtech's SmartDriverTM FET drive first pulls DH high with a pull-up resistance of 10 (typical) until LX = 1.5V (typical). At this point, an additional pull-up device is activated, reducing the resistance to 2 (typical). This negates the need for an external gate or boost resistor.
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SC475A
POWER MANAGEMENT Pin Configuration
DH NC G0 ILIM
Ordering Information
Device SC475AMLTRT(1) SC475AEVB
12 11 10 T 9 7 8
Package(2) MLPQ-16 3X3 Evaluation Board
16
15
14
13
LX BST VCC DL
1 2 3 4 5
TOP VIEW
EN PGOOD VOUT FB
Notes: 1) Available in tape and reel packaging only. A reel contains 3000 devices. 2) Available in lead-free packaging only. This product is fully WEEE, RoHS and J-TD-020B compliant. This component and all homogenous subcomponents are RoHS compliant.
6
GND
RTN
NC
MLPQ16: 3X3 16 LEAD
Marking Information
475A yyww xxxx
Marking for the 3x3mm MLPQ 16 Lead Package nnn = Part Number (Example: 475A) yyww = Date Code (Example: E652) xxxx = Semtech Lot No. (Example: E901)
(c) 2006 Semtech Corp.
D0
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SC475A
POWER MANAGEMENT Pin Descriptions
Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 T
Pin Name
LX BST VCC DL GND RTN NC D0 FB VOUT PGOOD EN ILIM G0 NC DH PAD
Pin Function
Switching (phase) node. Boost capacitor connection for high-side gate drive. 5V power input for the internal circuits and gate drive outputs. Gate drive output for the low-side external MOSFET. Power ground. This is the return point for the DL driver output, and the reference point for the ILIM and zero cross circuits. Return or analog ground for the FB input and FB resistor divider . Connect to GND directly at the IC. All feedback components should connect to this ground. Not connected internally -- leave unconnected or connect to GND. Drain of the internal MOSFET which is controlled by G0. Feedback sense point. The FB threshold is 0.75V; the resistor divider ratio between VOUT and FB sets the output voltage. This ratio can be modified using the G0 input to switch a resistor in or out at D0. Output voltage sense point for determining On-Time. Open-drain power good indicator - a high impedance indicates power is good. An external pull-up resistor is required. Enable input - connect EN to RTN to disable the SC475A. Current limit sense point -- to program the current limit connect a resistor from ILIM to LX or to a current sense resistor. Control input for the D0 MOSFET. A logic low energizes the D0 MOSFET, pulling D0 to ground. Not connected internally -- leave unconnected or connect to GND. Gate drive output for the high-side external MOSFET. Mounting pad. Not connected internally - connect to system ground plane through preferably one large vias or multiple smaller vias.
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SC475A
POWER MANAGEMENT Block Diagram
+5V
VBAT BST ILIM Valley I-Limit DH LX +5V
QB R
VCC UVLO 0.75V REF
S
DRV
Q
RTN
VOUT
DL
DRV
TON Predictor
VOUT
FB
D0 Control and Status
G0
EN
PGD
PAD
GND
+5V
Power Good
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SC475A
POWER MANAGEMENT Applications Information
SC475A Synchronous Buck Controller The SC475A is a synchronous power supply controller which simplifies the task of designing a dual-level power supply suitable for controlling video chip sets and other dual-voltage circuits. The SC475A provides an input (G0) which controls an internal pull-down transistor used to select from two adjustable output voltages. Battery and +5V Bias Supplies The SC475A requires an external +5V bias supply in addition to the VBAT supply. If stand-alone capability is required, the +5V bias supply can be generated with an external linear regulator. Pseudo-Fixed-Frequency Constant On-Time PWM Controller The PWM control method is a constant-on-time, pseudofixed-frequency PWM controller, see Figure 1. The ripple voltage seen across the output capacitor's ESR provides the PWM ramp signal, eliminating the need for a current sense resistor. The on-time is determined by an internal one-shot whose period is proportional to output voltage, and inversely proportional to input voltage. A separate oneshot sets the minimum off-time (typically 350ns).
VBAT TON VLX CIN VLX L Q2 ESR R1 FB + COUT R2
On-Time One-Shot (TON) The internal on-time one-shot comparator has two inputs. One input senses output voltage via the VOUT pin, while the other input samples VBAT via the LX pin and creates a proportional current which charges an internal capacitor. The TON time is the time required for this capacitor to charge from zero volts to VOUT, thereby making TON directly proportional to output voltage and inversely proportional to input voltage. This implementation results in a fairly constant switching frequency without the need of a clock generator. The internal frequency is optimized for 325kHz. The general equation for the on-time is: TON (nsec) = 2560 * (VOUT/VBAT) + 35 Immediately after the DH on-time, the DL output drives high to energize the low-side MOSFET. DL has a minimum high time of typically 350nsec, after which DL will continue to stay high until one of the following occur: * FB drops to the 0.75V reference * The Zero Cross detector trips if power save is active * The Negative Current Limit detector trips The Zero Cross detector monitors the voltage across the low-side MOSFET and trips when it reaches zero. If this occurs on eight consecutive cycles, then DL will subsequently shut off when the Zero Cross detector trips. See the PSAVE Operation section. Both MOSFETS will then stay off until FB drops to 0.75V, which will begin the next DH on-time. This is normal operation at light load. The Negative Current Limit detector trips when the drain voltage at the low-side MOSFET reaches typically +80mV, indicating a large negative current is being drawn through the inductor from VOUT. When this occurs, DL drives low. Both MOSFETS will then stay off until FB drops to 0.75V, which will begin the next DH on-time. Tripping the Negative Current detector is rare. If DL drives low because FB has dropped to the 0.75V reference, then another DH on-time is started: this is normal operation at heavy load. If DL drives low because of the
Q1
VFB
FB Threshold 0.75V VOUT
Figure 1
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SC475A
POWER MANAGEMENT Applications Information (continued)
Zero Cross detector, then both DH and DL will remain low until FB drops to the 0.75V reference, at which point the next DH on-time will begin. This is normal operation at light load. The typical operating frequency is 325kHz. It is possible to raise the frequency by placing a resistor divider between the output and the VOUT pin, see Figure 2. This reduces the voltage at the VOUT pin which is used to generate the on-time according to the previous equation. Note that this places a small minimum load on the output. The new frequency is approximated by the following equation: FREQ (kHz) = 325 (1 + R1/R2)
Power Output VOUT R1 pin 10 (VOUT) R2 1nF
VCC VLX L ESR + COUT 1nF R1 Power Output VOUT R2 pin 10 (VOUT)
Figure 3 VOUT Voltage Selection Output voltage is regulated by comparing VOUT as seen through a resistor divider to the internal 0.75V reference, see Figure 1. With D0 in the open state, the output voltage is at the lowest value and is set by the equation: VOUT = 0.75 * (1 + R1/R2) Voltage Transition Control The SC475A provides a G0 control input to allow selecting between two output voltages. The output voltage is regulated by comparing the FB pin (connected to VOUT via an external resistor divider) to the internal 0.75V reference. The G0 input controls the gate of an internal MOSFET whose source is connected to D0. Using G0 the user controls whether D0 is grounded or open, which then controls the resistor divider ratio for VOUT. A logic low signal on G0 will connect D0 to ground. When the G0 input changes state, this change quickly causes three actions:
1. D0 changes state. 2. The power good PGD output is temporarily latched into its present state. This prevents chattering or false tripping while VOUT moves to the new level. 3. The output over-voltage OVP point is raised to 50% above nominal, or 1.125V at FB. When going from a higher to lower voltage, the G0 change causes rapid change of D0, which in turns cause a rapid change at FB. The temporary increase in OVP allows the output to slew down to the new level without tripping the OVP function.
VLX L ESR + COUT
Figure 2 It is also possible to lower the frequency using a resistive divider to the 5V bias supply, see Figure 3. This raises the voltage at the VOUT pin which will increase the on-time. Note that this results in a small leakage path from the 5V supply to the output voltage. The resistor values should be fairly large (>50kOhm) large to prevent the output voltage from drifting up during shutdown conditions. Note that the feedback resistors act as a dummy load to limit how far the output can rise. The new operating frequency is approximated by the equation: FREQ (kHz) = 325 ((R1 + R2) / (R1 + R2 VCC/VOUT))
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SC475A
POWER MANAGEMENT Applications Information (continued)
VOUT Voltage Selection VOUT voltage is regulated through the FB pin via resistors R1 through R3 as shown in Figure 4. the output capacitor via the inductor. DL will remain on until FB falls to 0.75V, at which point a normal DH switching cycle begins, see Figure 5. This causes the output to transition to the new voltage level quickly, typically 10~20 usec. Refer to the Smart Power Save Protection section for a full description. A rapid downward change in VOUT also occurs for downward changes less than 8%, provided the load is high enough such that power-save is not active. In this case, after D0 opens and FB rises above the 0.75V trip point, DL will drive high and stay high until FB drops to the trip point.
VOUT R1 FB R2
R1 R3 FB TON 0.75V G0 Logic Control D0 R2 VOUT +
SC475A
R3
Figure 4 The following table shows the equations for VOUT as a function of control input G0:
D0
D0
RTN (Smart Psave threshold) 810mV 750mV (FB threshold)
VOUT Equation
0.75 * (1 + R1/R2) 0.75 * (1 + R1/R2 + R1/R3)
G0
1 0
DL FB
Note that the RDSON of the internal D0 mosfet is in series with R3, which adds typically 15 ohms in series.
DL
Voltage Transitioning The G0 pin allows VOUT to transition to both higher and lower values. The two directions have differing responses. When doing a down transition, the sudden release of R3 will cause FB to go above the 0.75V threshold. Depending on the level of VOUT change and the load, the IC responds in different ways. At light load conditions when power-save is active, and when the downward change is 8% or greater, the rapid change of D0 is large enough to cause FB to rise up to the Smart Power Save threshold (810mV). DL will then drive high to turn on the low-side MOSFET and draw current from
VOUT
Initial VOUT Final VOUT
Figure 5 For the case where the down transition is less than 8%, and the load is light such that power-save is active, the Smart Power Save detector will not activate. In this case, with FB already above the 0.75V reference there is no switching activity. DL and DH will remain off, and the output voltage will slowly fall as the output capacitors discharge into the load, see Figure 6.
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SC475A
POWER MANAGEMENT Applications Information (continued)
Note that at light loads it can take many msec for the output to fall to the new value. This should have no adverse effect. Many loads such as graphics chipsets can have a minimum load of several hundred mA, which will naturally pull VOUT down to the next level. When doing an up transition (from lower to higher VOUT), the G0 change affects D0 and causes FB to drop below the 0.75V trip point. This quickly trips the FB comparator regardless of whether psave is active or not, generating a DH on-time and a subsequent DL high time. At the end of the minimum off-time (350nsec), if FB is still below 0.75V then another DH on-time is started. This sequence continues until the FB pin exceeds 0.75V see Figure 7.
VOUT
R1 R3 D0 R2
D0 R2
VOUT
FB
R1 R3 FB
D0
RTN
(Smart Psave threshold) < 810mV
D0
FB 750mV (FB threshold) COUT Discharge due to load Initial VOUT Final VOUT
FB DH DL VOUT
RTN 750mV (FB threshold)
VOUT
Final VOUT Initial VOUT
Figure 6 For the case in Figure 6 the time needed to reach the final voltage is found from the following equation, where COUT is in F, and LOAD is in Amps: Time (sec) = COUT * (VINITIAL - VFINAL)/LOAD Note that the above equation only applies to the condition where the VOUT downward change is less that the 8% limit for Smart Psave, and also the load is light such that Psave is active. Figure 7 If the VOUT change is significant, there can be several consecutive cycles of DH on-time followed by minimum DL time. This can cause a rapid increase in inductor current: typically it only takes a few switching cycles for the inductor current to rise up to the Current Limit. At some point the FB voltage will rise up to the 0.75V reference and the DH pulses will cease, but the inductor's LI2 energy must then flow into the output cap. This can create a significant overshoot as shown in Figure 8.
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SC475A
POWER MANAGEMENT Applications Information (continued)
VOUT
CS R1 FB RS VOUT
R1 R3 D0 R2 FB
D0
R3
VS R2
CS
D0
D0
RTN 750mV (FB threshold)
FB
RTN 750mV (FB threshold)
FB
DH
DH DL Voltage overshoot VOUT Final VOUT Initial VOUT
DL
VOUT
Final VOUT Initial VOUT
Figure 8 The overshoot can be approximated by the following equation, where ICL is the current limit, VFINAL is the desired setpoint for the final voltage, L is in H and COUT is in F. VMAX = ( ICL2 * L/COUT + VFINAL2 ) This overshoot can be eliminated by using a small RC circuit to smooth the voltage seen at FB, see Figure 9. The presence of Rs/Cs will prevent the rapid changes at D0 from moving FB too quickly. The result is a gradual change from VOUTINITIAL to VOUTFINAL, to prevent the buildup of high inductor current and reducing overshoot. Note that Cs can be connected to either VOUT or GND. VOUT is preferred because this results in higher ripple seen at the FB pin, which improves stability.
Figure 9 Note that Rs/Cs are part of the FB resistor divider and therefore affect the output voltage sensing. To minimize the effect of this, select Rs and Cs according to the following guidelines: The total of Rs + R3 should be chosen to give the correct total resistance needed to adjust VOUT. Set Rs and R3 to the same value. Cs should be chosen to give a time constant equal to approximately 18sec for 325 kHz operation. Note that Cs is charging through a resistive network composed of Rs/R1/R2/R3. The effective resistance seen by Cs is roughly equal to the parallel combination of Rs and R3. For example, if the values for R1/R2/R3/Rs are 10k/50k/15k/15k, then the effective resistance would be (10k + 15k) paralleled with 15k, which is 9.4k. To set a time constant of 18sec, CS should be approximately 18sec/9.4k or 2000pF.
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SC475A
POWER MANAGEMENT Applications Information (continued)
Note that the presence of Rs/Cs will affect the effective resistance at the FB pin, and therefore modifies the VOUT setpoints. If Rs is used, the following table shows the calculated values for VOUT.
VOUT Equation
0.75 * (1 + R1/R2) 0.75 * (1 + R1/R2 + R1/(R3+Rs))
G0
1 0
Enable Input The EN is used to disable or enable the SC475A. When EN is low (grounded), the SC475A is off and in its lowestpower state. When EN is high the controller is enabled and switching will begin. PSAVE Operation The SC475A provides automatic power save operation at light loads. The internal Zero-Cross comparator looks for inductor current (via the voltage across the lower MOSFET) to fall to zero on eight consecutive switching cycles. Once observed, the controller enters power save and turns off the low-side MOSFET on each cycle when the current crosses zero. To add hysteresis, the on-time is increased by 25% in power save. The efficiency improvement at light loads more than offsets the disadvantage of slightly higher output ripple. If the inductor current does not cross zero on any switching cycle, the controller immediately exits power save. Since the controller counts zero crossings, the converter can sink current as long as the current does not cross zero on eight consecutive cycles. This allows the output voltage to recover quickly in response to negative load steps, or to voltage transitions from a higher to a lower voltage where the change exceeds 8%.
Smart Power Save Protection In some applications, active loads on VOUT can leak current from a higher voltage and thereby cause VOUT to slowly rise and reach the OVP threshold, causing a hard shutdown; the SC475A uses Smart Power Save to prevent this. When FB exceeds 8% above nominal (810mV), the IC exits power save (if already active) and DL drives high to turn on the low-side MOSFET, which starts to draw current from VOUT via the inductor. When FB drops to the 0.75V trip point, a normal TON switching cycle begins. This cycles energy from VOUT back to VBAT and prevents a hard OVP shutdown, and also minimizes operating power by avoiding continuous conduction-mode operation. If a light load is present, the switching continues for 8 consecutive clock cycles and then the IC will re-enter power save to reduce operating power. Current Limit Circuit Current limiting can be accomplished in two ways. The RDSON of the lower MOSFET can be used as a current sensing element, or a sense resistor at the lower MOSFET source can be used if greater accuracy is needed. RDSON sensing is more efficient and less expensive. In both cases, the RILIM resistor sets the over-current threshold. The RILIM connects from the ILIM pin to either the lower MOSFET drain (for RDSON sensing) or the high side of the current-sense resistor. RILIM connects to a 10A current source from the ILIM pin which turns on when the lowside MOSFET turns on, after the on-time DH pulse has completed. If the voltage drop across the sense resistor or low-side MOSFET exceeds the voltage across the RILIM resistor, current limit will activate. The high-side MOSFET is held off until the voltage drop across the sense element (resistor or MOSFET) falls below the voltage across the RILIM resistor. This current sensing scheme actually regulates the inductor valley current, (see Figure 10). This means that if the current limit is set to 10A, the peak current through the inductor would be 10A plus the peak ripple current, and the average current through the inductor would be 10A plus 1/2 the peak-to-peak ripple current.
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SC475A
POWER MANAGEMENT Applications Information (continued)
+5V VBAT
INDUCTOR CURRENT
I PEAK I LOAD I LIMIT
D1 Q1 BST DH LX ILIM VDD DL GND C2
+
C1
L1 Vout Q2 D2
+ C3
SC475A
R1 R4
TIME Valley Current Limit
Figure 10 The RDSON sensing circuit is shown in Figure 11 with RILIM = R1 and RDSON of Q2.
VBAT +5V
Figure 12 For resistor sensing, the current through the lower MOSFET and the source sense resistor develops a voltage that opposes the voltage developed across RILIM. When the voltage developed across the RSENSE resistor reaches voltage drop across RILIM, an over-current exists and the high-side MOSFET will not be allowed to turn on. The following over-current equation can be used for both RDSON or resistive sensing. For RDSON sensing, the MOSFET RDSON rating is used for the value of RSENSE.
RILIM RSENSE
D1
Q1
+
C1
BST DH LX ILIM VDD DL GND
C2
L VOUT
R1 Q2 D2 + C3
SC475A
IL OC Valley
10 A
Figure 11 The resistor sensing circuit is shown in Figure 12 with RILIM = R1 and RSENSE = R4
Power Good Output The power good (PGD) output is an open-drain output which requires a pull-up resistor. When the output voltage as sensed at FB is -20% from the 0.75V reference (600mV), PGD is pulled low. It is held low until the output voltage returns above -20% of nominal. PGD is held low during start-up and will not be allowed to transition high until soft-start is completed when FB reaches 0.75V. There is a 5s delay built into the PGD circuit to prevent false transitions.
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SC475A
POWER MANAGEMENT Applications Information (continued)
PGD also transitions low if the FB pin exceeds +20% of nominal, which is also the over-voltage shutdown point. When G0 changes state, PGD is immediately latched into its present state for 32 clock cycles while VOUT and FB change to the new level, after which the latch is disabled. Output Over-Voltage Protection In steady state operation, when FB exceeds 20% of nominal (900mV), DL latches high and the low-side MOSFET is turned on. DL stays high and the SMPS stays off until the EN/PSV input is toggled or VCC is recycled. There is a 5s delay built into the OVP detector to prevent false transitions. PGD is also held low after an OVP. During G0 transitions, the OVP threshold is temporarily increased to 50% above nominal (1.125V) for 32 clock cycles. This is for cases where the output voltage is slewing from a higher to a lower voltage: the change in G0 affects the D0 pin immediately, which in turn affects the FB voltage immediately. The increase in OVP from 20% to 50% is to prevent nuisance OVP tripping caused by the immediate change at FB. It also protects against the case of output overshoot for a lower to higher VOUT transition.
Note: since the temporary OVP is +50%, it is not possible to have a VOUT change which causes an immediate FB change of +50% or more. To transition VOUT under this condition, use the RC smoothing circuit to slow the FB transition edges and prevent +50% OVP.
Soft-Start The soft-start is accomplished by ramping the FB comparator's internal reference from zero to 0.75V in 30mV increments. Each 30mV step typically lasts for eight clock cycles. During the soft-start period, the Zero Cross Detector is active to monitor the voltage across the lower MOSFET while DL is high. If the inductor current reaches zero, the FB comparator's internal ramp reference is immediately overridden to match the voltage at the FB pin. This soon causes the FB comparator to trip which forces DL to turn off and the next DH on-time will begin. This prevents the inductor current from going too negative which would cause droop in the VOUT startup waveform. The next 30mV step on the internal reference ramp occurs from the new point at the FB pin. Since any of the internal 30mV steps can be overridden by the FB waveform, the startup time is dependent upon operating conditions. This override feature will stop when the FB pin reaches approximately 600mV, at which point the ramp resume 30mV steps up to 750mV. At start-up, during the first 32 switching cycles, the overcurrent threshold is reduced by 50%, to reduce overshoot caused by the first set of switching pulses. MOSFET Gate Drivers The DH and DL drivers are optimized for moderate, highside, and larger low-side power MOSFETs. An adaptive dead-time circuit monitors the DL output and prevents the high-side MOSFET from turning on until DL is fully off, and conversely, monitors the DH output and prevents the lowside MOSFET from turning on until DH is fully off.
Note: be sure there is low resistance and low inductance between the DH and DL outputs to the gate of each MOSFET.
Output Under-Voltage Protection When FB falls 30% below nominal (525mV) for eight consecutive clock cycles, the output is shut off; the DL/ DH drives are pulled low to tristate the MOSFETS, and the SMPS stays off until the Enable input is toggled or VCC is recycled. POR and UVLO Under-voltage lockout circuitry (UVLO) inhibits switching and tristates the DH/DL drivers until VCC rises above 4.4V. An internal power-on reset (POR) occurs when VCC exceeds 4.4V, which resets the fault latch and the softstart counter, to prepare the PWM for switching. At this time the SC475A will come out of UVLO and begin the soft-start cycle.
Design Procedure Prior to designing a switch mode supply, the input voltage, load current, switching frequency and inductor ripple current must be specified. For notebook systems the maximum input voltage (VINMAX) is determined by the highest AC adaptor voltage, and the minimum input voltage (VINMIN) is determined by the lowest battery voltage after accounting for voltage drops due to connectors, fuses and battery selector switches.
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SC475A
POWER MANAGEMENT Applications Information (continued)
In general, four parameters are needed to define the design: 1) Nominal output voltages (VOUT) 2) Static or DC output tolerance 3) Transient response 4) Maximum load current (IOUT) There are two values of load current to consider: continuous load current and peak load current. Continuous load current is concerned with thermal stresses which drive the selection of input capacitors, MOSFETs and diodes. Peak load current determines instantaneous component stresses and filtering requirements such as inductor saturation, output capacitors and design of the current limit circuit. Design example: * * * * VBAT = 10V min, 20V max VOUT1 = 0.9V +/- 4% VOUT2 = 1.15V +/-4% Load = 20A maximum must be defined. Smaller ripple current will give smaller output ripple and but will lead to larger inductors. The ripple current will also set the boundary for PSAVE operation. The switcher will typically enter PSAVE operation when the load current decreases to 1/2 of the ripple current; (i.e. if ripple current is 4A then PSAVE operation will typically start for loads less than 2A. If ripple current is set at 40% of maximum load current, then PSAVE will commence for loads less than 20% of maximum current). The equation for determining inductance is: L = (VBAT - VOUT) * TON / IRIPPLE Use the maximum value for VBAT, and for TON use the value associated with maximum VBAT. For selecting the inductor, we start with the highest VOUT setting and a maximum ripple current of 5A. TON = 182 nsec at 20VBAT, 1.15VOUT L = (20 - 1.15) * 182 nsec / 5A = 0.69H We will select a slightly larger value of 0.7H, which will decrease the maximum IRIPPLE to 4.91A.
Note: the inductor must be rated for the maximum DC load current plus 1/2 of the ripple current.
Inductor Selection Low inductor values result in smaller size but create higher ripple current. Higher inductor values will reduce the ripple current but are larger and more costly. Because wire resistance varies widely for different inductors and because magnetic core losses vary widely with operating conditions, it is often difficult to choose which inductor will optimize efficiency. The general rule is that higher inductor values have better efficiency at light loads due to lower core losses and lower peak currents, but at high load the smaller inductors are better because of lower resistance. The inductor selection is generally based on the ripple current which is typically set between 20% to 50% of the maximum load current. Cost, size, output ripple and efficiency all play a part in the selection process. The switching frequency is optimized for 325kHz. The equation for on-time is: TON (nsec) = 2560 * (VOUT/VBAT) + 35 During the DH on-time, voltage across the inductor is (VBAT - VOUT). To determine the inductance, the ripple current
The minimum ripple current under is also checked .This occurs when VBAT and VOUT are set to their minimum values of 10V and 0.9V. TONVBATMIN = 2560 * (0.9/10) + 35 = 265 nsec IRIPPLE = (VBAT - VOUT) * TON / L IRIPPLE_VBATMIN = (10 - 0.9) * 265 nsec / 0.7H = 3.45A Capacitor Selection The output capacitors are chosen based on required ESR and capacitance. The ESR requirement is driven by the output ripple requirement and the DC tolerance. The output voltage has a DC value that is equal to the valley of the output ripple, plus 1/2 of the peak-to-peak ripple.
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SC475A
POWER MANAGEMENT Applications Information (continued)
Change in the ripple voltage will lead to a change in DC voltage at the output. The design goal is +/-4% output regulation. The internal 0.75V reference tolerance is 1%, assuming 1% tolerance for the FB resistor divider, this allows 2% tolerance due to VOUT ripple. Since this 2% error comes from 1/2 of the ripple voltage, the allowable ripple is 4%, or 46mV for a 1.15V output. The maximum ripple current of 4.05A creates a ripple voltage across the ESR. The maximum ESR value allowed would create 46mV ripple: ESRMAX = VRIPPLE/IRIPPLEMAX = 46mV / 4.91A ESRMAX = 9.4 m The output capacitance is typically chosen based on transient requirements. A worst-case load release, from maximum load to no load at the exact moment when inductor current is at the peak, defines the required capacitance. If the load release is instantaneous (load changes from maximum to zero in a very small time), the output capacitor must absorb all the inductor's stored energy. This will cause a peak voltage on the capacitor according to the equation: COUTMIN = L * (IOUT + 1/2 * IRIPPLEMAX)2 / (VPEAK2 - VOUT2) With a peak voltage VPEAK of 1.230 (80mV rise above 1.15 upon load release), the required capacitance is: COUTMIN = 0.7H*(10 + 1/2*4.91)2/(1.242 - 1.152) COUTMIN = 570F The above requirements (570F, 9.4m) will be met using two capacitors, 330F 6m. If the load release is relatively slow, the output capacitance can be reduced. At heavy loads during normal switching, when the FB pin is above the 0.75V reference, the DL output is high and the low-side mosfet is on. During this time, the voltage across the inductor is approximately -VOUT. This causes a downslope or falling di/dt in the inductor. If the load di/dt is not much faster than the di/dt in the inductor, then the inductor current can track change in load current, and there will be relatively less overshoot from a load release. The following can used to calculate the needed capacitance for a given dILOAD/dt. Peak inductor current, ILPEAK = ILOADMAX + 1/2 * IRIPPLEMAX ILPEAK = 10 + 1/2 * 4.91 = 12.45A Rate of change of Load current = dILOAD/dt IMAX = maximum DC load current = 10A COUT = ILPEAK * (L *ILPEAK / VOUT - IMAX/dILOAD /dt) 2 * (VPEAK - VOUT) Example: Load dI/dt = 2.5A/sec This would cause the output current to move from 10A to zero in 4sec. COUT = 12.45*(0.7H*12.45/1.15 - 10/(2.5/1sec) 2 *(1.23 - 1.15) COUT = 278 F Stability Considerations Unstable operation shows up in two related but distinctly different ways: double-pulsing and fast-feedback loop instability. double-pulsing occurs due to switching noise seen at the FB input or because the ESR is too low, causing insufficient voltage ramp in the FB signal. This causes the error amplifier to trigger prematurely after the 350ns minimum off-time has expired. Double-pulsing will result in higher ripple voltage at the output but in most cases is harmless. In some cases, however, double-pulsing can indicate the presence of loop instability, which is caused by insufficient ESR. One simple way to solve this problem is to add some trace resistance between the VOUT/FB sense point and the output capacitor in the high current output path. A side effect of doing this is output voltage droop with load. Another way to eliminate doubling-pulsing is to add a small (e.g. 10pF) capacitor across the upper feedback resistor
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SC475A
POWER MANAGEMENT Applications Information (continued)
divider network, as shown in Figure 13. This capacitance should be left out until confirmation that double-pulsing exists. Adding this capacitance will add a zero in the transfer function and should eliminate the problem. It is best to leave a spot on the PCB in case it is needed. exceeds the off-time of the converter. To prevent double pulsing, the ripple voltage present at the FB pin should be 10-15mV minimum over the on-time interval. Dropout Performance The VOUT adjust range for continuous-conduction operation is limited by the fixed 350nsec (typical) Minimum Off-time One-shot. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times. The IC duty-factor limitation is given by: DUTY = TONMIN/(TONMIN + TOFFMAX)
SC475A
R1 R3 C FB TON 0.75V G0
Logic Control
VOUT +
D0
R2
Figure 13 Loop instability can cause oscillations at the output as a response to line or load transients. These oscillations can trip the over-voltage protection latch or cause the output voltage to fall below the tolerance limit. The best way for checking stability is to apply a zero-tofull load transient and observe the output voltage ripple envelope for overshoot and ringing. Over one cycle of ringing after the initial step is a sign that the ESR should be increased. SC475A ESR Requirements The constant on-time control used in the SC475A regulates the valley of the output ripple voltage. This signal consists of a term generated by the output ESR of the capacitor and a term based on the increase in voltage across the capacitor due to charging and discharging during the switching cycle. The minimum ESR is set to generate the required ripple voltage for regulation. For most applications the minimum ESR ripple voltage is dominated by PCB layout and the properties of SP or POSCAP type output capacitors. For applications using ceramic output capacitors, the absolute minimum ESR must be considered. If the ESR is low enough the ripple voltage is dominated by the charging of the output capacitor. This ripple voltage lags the on-time due to the LC poles and can cause double pulsing if the phase delay
Be sure to include inductor resistance and MOSFET onstate voltage drops when performing worst-case dropout duty-factor calculations. SC475A System DC Accuracy (VOUT Controller) Three factors affect VOUT accuracy: the trip point of the FB error comparator, the switching frequency variation with line and load, and the external resistor tolerance. The error comparator offset is trimmed to trip when the feedback pin is 0.75V, +/-1%. The on-time pulse in the SC475A is calculated to give a pseudo-fixed frequency of 325kHz. Nevertheless, some frequency variation with line and load is expected. This variation changes the output ripple voltage. Because constant on-time converters regulate to the valley of the output ripple, 1/2 of the output ripple appears as a DC regulation error. For example, If the output ripple is 50mV with VIN = 6 volts, then the measured DC output will be 25mV above the comparator trip point. If the ripple increases to 80mV with VIN = 25 volts, then the measured DC output will be 40mV above the comparator trip. The best way to minimize this effect is to minimize the output ripple. To compensate for valley regulation it is often desirable to use passive droop. Take the feedback directly from the output side of the inductor, placing a small amount of trace resistance between the inductor and output capacitor. This trace resistance should be optimized so that at full load the output droops to near the lower regulation limit.
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SC475A
POWER MANAGEMENT Applications Information (continued)
Passive droop minimizes the required output capacitance because the voltage excursions due to load steps are reduced. The use of 1% feedback resistors contributes typically 1% error. If tighter DC accuracy is required use 0.1% resistors. The output inductor value may change with current. This will change the output ripple and thus the DC output voltage. The output ESR also affects the ripple and thus the DC output voltage. Switching Frequency Variations The switching frequency will vary somewhat due to line and load conditions. The line variations are a result of a fixed offset in the on-time one-shot, as well as unavoidable delays in the external MOSFET switching. As VBAT increases, these factors make the actual DH on-time slightly longer than the idealized on-time. The net effect is that frequency tends to fall slightly with increasing input voltage. The load variations are due to losses in the power train from IR drop and switching losses. For a conventional PWM constant-frequency topology, as load increases the duty cycle also increases slightly to compensate for IR and switching losses in the MOSFETs and inductor. A constant on-time topology must also overcome the same losses by increasing the duty cycle (more time is spent drawing energy from VBAT as losses increase). Since the on-time is constant for a given VOUT/VBAT combination, the way to increase duty cycle is to gradually shorten the off-time. The net effect is that switching frequency increases slightly with increasing load. Layout Guidelines One or more ground planes are recommended to minimize the effect of switching noise and copper losses and to maximize heat removal. The analog ground reference, RTN, should connect directly to the thermal pad, which in turn connects to the ground plane through preferably one large via. There should be a RTN plane or copper are near the chip; all components that are referenced to RTN should connect to this plane directly, not through the ground plane, and located on the chip side of the PCB if possible. GND should be a separate plane which is not used for routing analog traces. The VCC input provides power to the internal analog circuits and the upper and lower gate drivers. The VCC supply decoupling capacitor should be tied between VCC and GND with short traces. All power GND connections should connect directly to this plane with special attention given to avoiding indirect connections between RTN and GND which will create ground loops. As mentioned above, the RTN plane must be connected to the GND plane at the chip near the RTN/GND pins. The switcher power section should connect directly to the ground plane(s) using multiple vias as required for current handling (including the chip power ground connections). Power components should be placed to minimize loops and reduce losses. Make all the power connections on one side of the PCB using wide copper filled areas if possible. Do not use "minimum" land patterns for power components. Minimize trace lengths and maximize trace widths between the gate drivers and the gates of the MOSFETs to reduce parasitic impedances (and MOSFET switching losses); the low-side MOSFET is most critical. Maintain a length to width ratio of <20:1 for gate drive signals. Use multiple vias as required by current handling requirement (and to reduce parasitic) if routed on more than one layer. For an accurate ILIM current sense connection, connect the ILIM trace to the current sense element (MOSFET or resistor) directly at the pin of the element, and route that trace over to the ILIM resistor on another layer if needed. The layout can be generally considered in two parts; the analog control section referenced to RTN, and the switcher power section referenced to GND.
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SC475A
POWER MANAGEMENT Applications Information (continued)
Looking at the control section first, locate all components referenced to RTN on the schematic and place these components near the chip and on the same side if possible. Connect RTN using a wide trace. Very little current flows in the RTN path and therefore large areas of copper are not needed. Connect the RTN pin directly to the thermal pad under the device as the only connection between RTN and GND. The chip supply decoupling capacitor (VCC/GND) should be located near to the pins. Since the DL pin is directly between VCC and GND, and the DL trace must be a wide, direct trace, the VCC decoupling capacitor is best placed on the opposite side of the PCB, routed with traces as short as possible and using at least two vias when connecting through the PCB. There are two sensitive, feedback-related pins at the chip: VOUT and FB. Proper routing is needed to keep noise away from these signals. All components connected to FB should be located directly at the chip, and the copper area of the FB node minimized. The VOUT trace that feeds into the VOUT pin, which also feeds the FB resistor divider, must be kept far away from noise sources such as switching nodes, inductors and gate drives. Route the VOUT trace in a quiet layer if possible, from the output capacitor back to the chip. For the switcher power section, there are a few key guidelines to follow: 1) There should be a very small input loop between the input capacitors, MOSFETs, inductor, and output capacitors. Locate the input decoupling capacitors directly at the MOSFETs. 2) The phase node should be a large copper pour, but still compact since this is the noisiest node. 3) The power GND connection between the input capacitors, low-side MOSFET, and output capacitors should be as small as is practical, with wide traces or planes. 4) The impedance of the power GND connection between the low-side MOSFET and the GND pin should be minimized. This connection must carry the DL drive current, which has high peaks at both rising and falling edges. Use mulitple layers and multiple vias to minimize impedance, and keep the distance as short as practical. Finally, connecting the control and switcher power sections should be accomplished as follows: 1) Route the VOUT/FB feedback traces in a "quiet" layer, away from noise sources. 2) Route DL, DH and LX (low side FET gate drive, high side FET gate drive and phase node) to the chip using wide traces, with multiple vias if using more than one layer. These connections are to be as short as possible for loop minimization, with a length to width ratio less than 20:1 to minimize impedance. DL is the most critical gate drive, with power GND as its return path. LX is the noisiest node in the circuit, switching between VBAT and ground at high frequencies, thus should be kept as short as practical. DH has LX as its return path. DL, DH, LX, and BST are highnoise signals and should be kept well away from sensitive signals, particularly FB and VOUT. 3) BST is also a noisy node and should be kept as short as possible. The high-side DH driver is relies on the boost capacitor to provide the DH drive current, so the boost capacitor must be placed near the IC and connect to the BST and LX pins using short, wide traces to minimize impedance. 4) Connect the GND pin on the chip to the VCC decoupling capacitor and then drop vias directly to the ground plane. Locate the current limit resistor RLIM at the chip with a kelvin connection to the drain of the lower MOSFET at the phase node, and minimize the copper area of the ILIM trace.
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SC475A
POWER MANAGEMENT Typical Characteristics
TON vs. VBAT - VOUT > 2.5V
2600 2400 2200 2000
TON vs. VBAT - VOUT < 1.8V
1000 900 800
TON (nsec)
1600 1400 1200 1000 800 600 400 200 5 10
2.5V 3.3V
TON (nsec)
1800
5V
700 600 500 400 300 200 100
0.75V 1.1V 1.5V 1.8V
15
20
5
10
15
20
VBAT (V)
VBAT (V)
Frequency vs. BAT
400 390 380 370
Frequency (kHz)
1.8V 1.5V
Efficiency vs. Load - VOUT = 1.15V
95%
10V
90%
1.25V
360 350 340 330
1.1V
Efficiency (%)
15V
85%
19V
320 310 300 5 7 9 11
80%
1.0V 0.9V 0.75V
13 15 VBAT (V)
17
19
21
23
75% 0
2
4
6
8
10
12
14
16
18
20
Load (A)
Load Regulation
1.18
1.18
Line Regulation
3A
1.17
19V
1.17
No Load
1.16
VOUT (V)
1.16
1.15
VOUT (V)
10V 15V
1.15
10A
1.14
1.14
15A
1.13
1.13
1.12 0 2 4 6 8 10 12 14 16 18 20
1.12 10 12 14 16 18
Load (A)
VBAT (V)
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SC475A
POWER MANAGEMENT Typical Characteristics (continued)
Startup 1.15V 19VBAT No load Startup 1.15V 19VBAT 20A load
Load Transient Response 0A to 20A
Load Transient Response 20A to 0A
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SC475A
POWER MANAGEMENT Typical Characteristics (continued)
VOUT Up Transition VOUT = 0.9 to 1.15V, VBAT = 15V 1A Load VOUT Up Transition VOUT = 0.9 to 1.15V, VBAT = 15V 15A Load
VOUT Down Transition VOUT = 1.15 to 0.9V, VBAT = 15V 1A Load
VOUT Down Transition VOUT = 1.15 to 0.9V, VBAT = 15V 15A Load
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SC475A
POWER MANAGEMENT Reference Design
VBAT EN VCC G0 C1 10UF C2 10UF C3 10UF D1 BAT54A R3 10K R7 10K ILIM PGD VOUT VCC
Q1
RJK0305DP
1 2 3
5 6 7 8 9
D
4
16
15
14 G0
VOUT
DH
NC
0.7uH
L1
LX
ILIM
C4 100NF
1 2 3 4 4 17
13
5 6 7 8 9
LX BST VCC
EN
12 11 10 9 PGD VOUT FB R16 15K R11 15K R8 10K
VCC
D
U1 SC475A
RTN NC
C
PGD VOUT FB
C6 NO_POP
+ C5*
+ C6*
GND
1 2 3
Q2
RJK0302DP
C8 1UF
PAD
D0
C7 1UF
D2 MBRS140L
DL
A
C12 10nF
R12 49.9K
5
6
7
330uF/6mohm
8
C9 2200PF
Reference Design -- 0.90V/1.15V 20A
Bill of Materials
Component C1, C2, C3 Value Manufacturer Part Number Web
10uF, 25V 330uF/6mohm/2V 0.7uH, 24A 10mohm/30V 3.5mohm/30V 200mA/30V 1A/40V
Murata Panasonic NEC Tokin Renesas Renesas OnSemi OnSemi
GRM32DR71E106KA12L EEFSX0D331XR C-PI-1350-0R7S RJK0305DBP RJK0302DBP BAT54C MBSR140LT3
www.murata.com www.panasonic.com http://www.nec-tokin.com www.renesas.com www.renesas.com www.onsemi.com www.onsemi.com
C5, C5 L1 Q1 Q2 D1 D2
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SC475A
POWER MANAGEMENT Outline Drawing - MLPQ-16 3 x 3
A
D
B
DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX
A A1 A2 b D D1 E E1 e L N aaa bbb .031 .040 .000 .002 (.008) .007 .009 .012 .114 .118 .122 .061 .067 .071 .114 .118 .122 .061 .067 .071 .020 BSC .012 .016 .020 16 .003 .004 0.80 1.00 0.00 0.05 (0.20) 0.18 0.23 0.30 2.90 3.00 3.10 1.55 1.70 1.80 2.90 3.00 3.10 1.55 1.70 1.80 0.50 BSC 0.30 0.40 0.50 16 0.08 0.10
PIN 1 INDICATOR (LASER MARK)
E
A2 A aaa C A1 C D1 e/2 LxN E/2 E1
2 1 N
SEATING PLANE
e bxN D/2
NOTES: 1. 2. 3. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DAP IS 1.90 x 1.90mm.
bbb
CAB
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SC475A
POWER MANAGEMENT Land Pattern - MLPQ-16 3 x 3
H R
DIM
(C) K G Z
DIMENSIONS INCHES MILLIMETERS
(.114) .083 .067 .067 .020 .006 .012 .031 .146 (2.90) 2.10 1.70 1.70 0.50 0.15 0.30 0.80 3.70
Y
X P
NOTES: 1.
C G H K P R X Y Z
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 Fax: (805) 498-3804
www.semtech.com
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